Differential signals are commonly used in electronic circuits and systems. In information-carrying signals, the use of differential signals provides the opportunity to apply noise-canceling techniques. In clocking signals, differential clocks are commonly used to provide high-speed switching capabilities.
The use of differential signaling typically requires complementary symmetry between the pair of differential signals, including coincident switching. An offset of switching time between the pair of differential signals is termed “skew”, and low-skew circuits are preferred for optimal differential signal processing, particularly at high speeds.
FIG. 1 illustrates a conventional circuit for converting a single-ended signal In into a pair of differential signals Q, Qn. The pair of inverters 110, 120 provide an output Q that is in phase with the input signal In, and the single inverter 130 provides an output Qn that is out of phase with the input signal In, and thus out of phase with the output Q. The skew of this circuit corresponds to the difference between the propagation time though the pair of inverters 110, 120 and the propagation time though the single inverter 130. Nominally, the skew of the circuit of FIG. 1 is equal to one inverter delay duration, because the output Qn transitions after one inverter delay, and output Q transitions after two inverter delays. Techniques can be applied to size the components of the inverters 110, 120, 130 to reduce the transition speed of inverter 130 compared to the inverters 110, 120, but such techniques typically exhibit a strong dependency on process, voltage, and temperature (PVT) parameters to achieve low-skew. Additionally, in a CMOS embodiment, the 0-to-1 and 1-to-0 transition characteristics will also vary differently over PVT variations.
The circuit of FIG. 2 reduces the skew of the circuit of FIG. 1 by placing an inverter 240 between the output Q and the output Qn. During a transition of the input In, the output of the inverter 130 tries to change immediately, but the inverter 240 holds the prior state, because the transition has not yet propagated through inverters 110, 120. Thus, the inverter 240 delays the transition of the output Qn, thereby reducing the transition delay to less than one inverter delay. Although the circuit of FIG. 2 exhibits a lower skew, it draws more power than the circuit of FIG. 1, particularly in a CMOS embodiment, because the conflicting states of the inverters 130 and 240 keeps the inverter 130 in the active region during the delayed transition of the output Qn. The circuit of FIG. 2 also exhibits poor consistency over a range of PVT parameters.
The circuit of FIG. 3 exhibits fairly low skew, provided that the exclusive-nor gates 310, 320 can be designed with symmetric 0-to-1 and 1-to-0 transition delay characteristics. However, achieving such symmetry is difficult, particularly over a range of PVT parameters.
U.S. Pat. No. 5,945,878, “SINGLE-ENDED TO DIFFERENTIAL SIGNAL CONVERTER”, issued 31 Aug. 1999 to Westwick et al., and incorporated by reference herein, illustrates a low-skew converter, as illustrated in FIG. 4. In this embodiment, a common-gate transistor 410 is used to provide the in-phase output Q, and a common-source transistor 420 is used to provide the out-of-phase output Qn. The sizes of the devices 410, 420 and the bias current are controlled to provide equal transimpedances through each of the devices 410, 420 to provide symmetric outputs Q, Qn. The circuit of FIG. 4 provides low skew, but it employs coupling capacitors that limit its application to dynamic circuits, and cannot be used for static circuits. Additionally, it cannot be driven by rail-to-rail CMOS logic transitions.